The time division multiplex format commonly utilised in UK takes the form of a frame which provides time-slots for 30 digital channels, i.e. 30 traffic slots. In addition the frame has a slot, identified as "slot 0" for synchronisation and a "slot 16", i.e. the seventeenth in the sequence, which is used for signalling (that is indicating the start and end of calls and identifying numbers called to the exchange). Thus there are 32 slots in each frame.
It is also an accepted practice for a public "common carrier" of telecommunications to connect suitable customers to the public switched network via a multiplexed channel using the standard 32 slots even when the customer does not need the 30 channels provided by 30 slots. In those circumstances the operation is controlled so that only assigned slots are used.
The interface according to the invention is capable of operating with a wide range of external stations and, in particular, it is adaptable to whatever proportion of the multiplex frame is assigned to a particular external station.
A preferred interface means provides three functions; thus it comprises:
(a) A first channel for accepting digital signals in time division multiplex format and providing said signals to a TDMA; PA0 (b) A duplex channel for re-constituting signals received via TDMA into an assigned time division multiplex format; and PA0 (c) TDMA circuitry for participating in the operation of a TDMA system, said TDMA circuitry being operatively connected to items (a) and (b) above to provide synchronisation and compatability between the signals in said channels and the TDMA.
The first channel conveniently comprises gate-means for selecting defined slots from received frames, buffer means for storing said selected slots and burst forming means for concatenating TDMA information with the stored slots to produce a burst. The gate-means preferably comprises a frame-counter responsive to the sync slot in each frame of a received multiplexed signal wherein said frame-counter is operatively connected to a frame map store and a buffer input gate and a channel map store in such a manner that the frame-counter activates the buffer input gate to permit the passage of a byte when its count matches a value retained in the channel map store.
The duplex channel conveniently includes a reception buffer for storing received bursts, an output buffer for storing regenerated frames and frame regeneration means for transferring bytes from the reception buffer to the output buffer and for incorporating blank slots in accordance with synchronisation markers contained in said received bursts to reconstitute the specified frames.
Preferably the duplex channel also includes a slot control counter operatively linked to the channel map store to control a frame gate to pass either bytes from the reception buffer to the output buffer or to pass blank slots to the output buffer and a synchronisation detector for synchronising the count of the slot control counter with synchronisation bytes provided by the reception buffer wherein said synchronisation detector is responsive to output of the frame gate.
The TDMA circuitry conforms to the requirements of the TDMA system. In particular the interface circuitry of this invention is compatible with the TDMA system disclosed in our earlier patent application as follows:
______________________________________ APPLICATION APPLICATION NUMBER DATE ______________________________________ EPO 84306111 6 September 1984 Canada 462307 31 August 1984 Japan 84-188765 7 September 1984 USA 647441 5 September 1984 ______________________________________
In this specification references to "our earlier application" means the applications specified above.
Our earlier application is characterised in that the communication, in both directions, takes the form of a sequence of traffic bursts wherein each traffic burst includes a marker for synchronisation. It is a particular feature that each active outstation utilises synchronisation markers only in its own bursts. On receipt of a burst an active outstation initiates a pre-set delay and it returns a burst to the node. The node has control of all the outstations and it adjusts each pre-set delay so that bursts received at the node are in the correct sequence.
The outstations require clocks which are used, in conjunction with the markers, to keep synchronisation. As described in our earlier application, the node has control of the synchronisation of the system because (a) all clocks are derived from a master clock at the node, (b) the phasing of the clocks is fixed by synchronisation markers transmitted by the node and (c) the pre-set delays are adjusted by the node.
The outstations of our earlier application are synchronised to transmit in turn. Since it is unwise to rely on perfect adjustment the synchronisation is designed with gaps to reduce the occurrence of overlaps. There will be large gaps when outstations do not wish to transmit (and there will be complete silence when no outstation wishes to transmit). Thus the reception at the node has a discontinuous burst structure.
As our earlier application points out the information bearing transmissions from the node have a similar discontinuous burst structure but clocks dependant on the node would cease to function during gaps and this could have an adverse effect on system performance. It is, therefore, desirable that the node generates a randomised pseudo-signal which is used to fill the gaps between information-containing bursts. Thus the transmission from the node has a discontinuous burst structure in respect of the information bearing content but the discontinuities are filled with timing signal whereby dependant clocks are kept in adjustment.